Featuring a low jitter of 0.36 ps rms, the MAX3624/MAX3625 quad-/triple-output clock generators a high-frequency clock signal from a low-frequency crystal resonator or reference clock input. The MAX3624 provides four outputs from two output divider banks: one bank provides two LVPECL outputs up to 320 MHz; the other provides one LVPECL output up to 320 MHz and one LVCMOS output up to 160 MHz.
The MAX3625 provides three outputs from two output divider banks: one bank provides two LVPECL outputs up to 320 MHz; the other bank provides one LVPECL output up to 320 MHz. The MAX3624 is fully specified over the 0 to 85C extended temperature range, operates from 3.3 V ±5%, and is housed in a 32-pin TQFN package. The MAX3625 is fully specified over the 0 to 70°C temperature range, operates from 3.3 V ±5%, and is housed in a 24-pin TSSOP package.
