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PIC12C5XX

8-Pin, 8-Bit CMOS Microcontrollers

Devices included in this Data Sheet:
. 
PIC12C508 . PIC12C508A . PIC12CE518

. 
PIC12C509 . PIC12C509A . PIC12CE519

. 
PIC12CR509A

Note: Throughout this data sheet PIC12C5XX refers to the PIC12C508, PIC12C509, PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518 and PIC12CE519. PIC12CE5XX refers to PIC12CE518 and PIC12CE519.
High-Performance RISC CPU:
. 
Only 33 single word instructions to learn

. 
All instructions are single cycle (1 ¦Ì s) except for program branches which are two-cycle

. 
Operating speed: DC - 4 MHz clock input DC - 1 ¦Ì s instruction cycle

. 
12-bit wide instructions

. 
8-bit wide data path

. 
Seven special function hardware registers

. 
Two-level deep hardware stack

. 
Direct, indirect and relative addressing modes for data and instructions

. 
Internal 4 MHz RC oscillator with programmable calibration

. 
In-circuit serial programming

Device  Memory 
EPROM Program  ROM Program  RAM Data  EEPROM Data 
PIC12C508  512 x 12  25 
PIC12C508A  512 x 12  25 
PIC12C509  1024 x 12  41 
PIC12C509A  1024 x 12  41 
PIC12CE518  512 x 12  25  16 
PIC12CE519  1024 x 12  41  16 
PIC12CR509A  1024 x 12  41 

Peripheral Features:
. 
8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler

. 
Power-On Reset (POR)

.
Device Reset Timer (DRT)

. 
Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

. 
Programmable code-protection

. 
1,000,000 erase/write cycle EEPROM data  memory

. 
EEPROM data retention > 40 years

. 
Power saving SLEEP mode

. 
Wake-up from SLEEP on pin change

. 
Internal weak pull-ups on I/O pins

. 
Internal pull-up on MCLR pin

. 
Selectable oscillator options: -INTRC: Internal 4 MHz RC oscillator -EXTRC: External low-cost RC oscillator -XT: Standard crystal/resonator -LP: Power saving, low frequency crystal

CMOS Technology:
. 
Low power, high speed CMOS EPROM/ROM technology

. 
Fully static design

. 
Wide operating voltage range

. 
Wide temperature range:

- Commercial: 0¡ãC to +70¡ãC
-Industrial: -40¡ãC to +85¡ãC
-Extended: -40¡ãC to +125¡ãC

. 
Low power consumption

-
< 2 mA @ 5V, 4 MHz

-
 15 ¦Ì A typical @ 3V, 32 KHz

-
 < 1 ¦Ì A typical standby current

PIC12C5XX

Pin Diagram - PIC12C508A/509A, PIC12CE518/519

Pin Diagram - PIC12CR509A

Device Differences
Device  Voltage Range  Oscillator  Oscillator Calibration2 (Bits)  Process Technology (Microns) 
PIC12C508A PIC12LC508A  3.0-5.5 2.5-5.5  See Note 1 See Note 1  6 6  0.7 0.7 
PIC12C508  2.5-5.5  See Note 1  4  0.9 
PIC12C509A PIC12LC509A  3.0-5.5 2.5-5.5  See Note 1 See Note 1  6 6  0.7 0.7 
PIC12C509  2.5-5.5  See Note 1  4  0.9 
PIC12CR509A  2.5-5.5  See Note 1  6  0.7 
PIC12CE518  3.0-5.5  - 6  0.7 
PIC12LCE518  2.5-5.5  - 6  0.7 
PIC12CE519  3.0-5.5  - 6  0.7 
PIC12LCE519  2.5-5.5  - 6  0.7 

Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, please verify oscillator characteristics in your application.
Note 2: See Section 7.2.5 for OSCCAL implementation differences.

PIC12C5XX

TABLE OF CONTENTS

1.0 
General Description...............................................................................................................................................4

2.0 PIC12C5XX Device Varieties ................................................................................................................................ 7

3.0 Architectural Overview........................................................................................................................................... 9

4.0 Memory Organization .......................................................................................................................................... 13

5.0 I/O Port ................................................................................................................................................................ 21

6.0 Timer0 Module and TMR0 Register .................................................................................................................... 25

7.0 EEPROM Peripheral Operation...........................................................................................................................29

8.0 Special Features of the CPU...............................................................................................................................35

9.0 Instruction Set Summary ..................................................................................................................................... 47

10.0 Development Support..........................................................................................................................................59

11.0 Electrical Characteristics -PIC12C508/PIC12C509............................................................................................65

12.0 DC and AC Characteristics - PIC12C508/PIC12C509 ........................................................................................ 75

13.0 Electrical Characteristics  PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/ PIC12CE518/PIC12CE519/ PIC12LCE518/PIC12LCE519/PIC12LCR509A................................................................................................... 79
14.0 DC and AC Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/ PIC12LCE518/PIC12LCE519/ PIC12LCR509A .................................................................................................. 93
15.0
Packaging Information.........................................................................................................................................99
Index ........................................................................................................................................................................... 105
PIC12C5XX Product Identification System ................................................................................................................ 109
Sales and Support: ..................................................................................................................................................... 109

To Our Valued Customers
Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number.  e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
.
Microchip¡¯s Worldwide Web site; http://www.microchip.com

.
Your local Microchip sales office (see last page)

.
The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Corrections to this Data Sheet

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.
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.
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We appreciate your assistance in making this a better document.

PIC12C5XX

1.0 GENERAL DESCRIPTION
The PIC12C5XX from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EEPROM/EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1 ¦Ì s) except for program branches which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly.
The PIC12C5XX products are equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features also improve system cost, power and reliability.
The PIC12C5XX are available in the cost-effective One-Time-Programmable (OTP) versions which are suitable for production in any volume. The customer
can take full advantage of Microchip¡¯s price leadership in OTP microcontrollers while benefiting from the OTP¡¯s flexibility.
The PIC12C5XX products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ¡®C¡¯ compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM. PC and compatible machines.
1.1 Applications
The PIC12C5XX series fits perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The EPROM technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient, while the EEPROM data memory technology allows for the changing of calibration factors and security codes. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC12C5XX series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of ¡°glue¡± logic and PLD¡¯s in larger systems, coprocessor applications).

PIC12C5XX

TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES
PIC12C508(A)  PIC12C509(A)  PIC12CR509A  PIC12CE518  PIC12CE519  PIC12C671  PIC12C672  PIC12CE673  PIC12CE674 
Maximum  4  4  4  4  4  10  10  10  10 
Clock  Frequency of Operation 
(MHz) 
EPROM  512 x 12  1024 x 12  1024 x 12  512 x 12  1024 x 12  1024 x 14  2048 x 14  1024 x 14  2048 x 14 
Program  (ROM) 
Memory  Memory 
RAM Data  25  41  41  25  41  128  128  128  128 
Memory 
(bytes) 
EEPROM  ¡ª  ¡ª  ¡ª  16  16  ¡ª  ¡ª  16  16 
Data Memory 
Peripherals  (bytes) 
Timer Module(s)  TMR0  TMR0  TMR0  TMR0  TMR0  TMR0  TMR0  TMR0  TMR0 
A/D Con ¡ª  ¡ª  ¡ª  ¡ª  ¡ª  4  4  4  4 
verter (8-bit) 
Channels 
Wake-up  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
from SLEEP
 on pin 
Features  change 
Interrupt Sources  ¡ª  ¡ª  ¡ª  4  4  4  4 
I/O Pins  5  5  5  5  5  5  5  5  5 
Input Pins  1  1  1  1  1  1  1  1  1 
Internal Pull-ups  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
In-Circuit  Yes  Yes  ¡ª  Yes  Yes  Yes  Yes  Yes  Yes 
Serial 
Programming 
Number of Instructions  33  33  33  33  33  35  35  35  35 
Packages  8-pin DIP,  8-pin DIP,  8-pin DIP,  8-pin DIP,  8-pin DIP,  8-pin DIP,  8-pin DIP,  8-pin DIP,  8-pin DIP, 
JW, SOIC  JW, SOIC  SOIC  JW, SOIC  JW, SOIC  JW, SOIC  JW, SOIC  JW  JW 

All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.

PIC12C5XX

NOTES:

PIC12C5XX

2.0 PIC12C5XX DEVICE VARIETIES
A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12C5XX Product Identification System at the back of this data sheet to specify the correct part number.
2.1 UV Erasable Devices
The UV erasable version, offered in ceramic side brazed package, is optimal for prototype development and pilot programs.
The UV erasable version can be erased and reprogrammed to any of the configuration modes.
Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.
Microchip¡¯s PICSTART. PLUS and PRO MATE. programmers all support programming of the PIC12C5XX. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources.
2.2 One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications.
The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
2.3 Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
2.5 Read Only Memory (ROM) Device
Microchip offers masked ROM to give the customer a low cost option for high volume, mature products.

PIC12C5XX

NOTES:

PIC12C5XX

3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC12C5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C5XX uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions
(33) execute in a single cycle (1¦Ì s @ 4MHz) except for program branches.
The table below lists program memory (EPROM), data memory (RAM), ROM memory, and non-volatile (EEPROM) for each device.
Device  Memory 
EPROM Program  ROM Program  RAM Data  EEPROM Data 
PIC12C508  512 x 12  25 
PIC12C509  1024 x 12  41 
PIC12C508A  512 x 12  25 
PIC12C509A  1024 x 12  41 
PIC12CR509A  1024 x 12  41 
PIC12CE518  512 x 12  25 x 8  16 x 8 
PIC12CE519  1024 x 12  41 x 8  16 x 8 

The PIC12C5XX can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC12C5XX has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature
and lack of ¡®special optimal situations¡¯ make programming with the PIC12C5XX simple yet efficient. In addition, the learning curve is reduced significantly.
The PIC12C5XX device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWFand ADDWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

PIC12C5XX

PIC12C5XX

TABLE 3-1: PIC12C5XX PINOUT DESCRIPTION
Name  DIP Pin #  SOIC Pin #  I/O/P Type  Buffer Type  Description 
GP0  7  7  I/O  TTL/ST  Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. 
GP1  6  6  I/O  TTL/ST  Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. 
GP2/T0CKI  5  5  I/O  ST  Bi-directional I/O port. Can be configured as T0CKI. 
GP3/MCLR/VPP  4  4  I  TTL/ST  Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter programming mode. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull-up always on if configured as MCLR. ST when in MCLR mode. 
GP4/OSC2  3  3  I/O  TTL  Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes). 
GP5/OSC1/CLKIN  2  2  I/O  TTL/ST  Bidirectional IO port/oscillator crystal input/external clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode. 
VDD  1  1  P  ¡ª  Positive supply for logic and I/O pins 
VSS  8  8  P  ¡ª  Ground reference for logic and I/O pins 

Legend: I = input, O = output, I/O = input/output, P = power, ¡ª = not used, TTL = TTL input, ST = Schmitt Trigger input
PIC12C5XX

3.1 Clocking Scheme/Instruction Cycle
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.
3.2 Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1).
A fetch cycle begins with the program counter (PC) incrementing in Q1.
In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1.
 MOVLW 03H

2.
 MOVWF GPIO

3.
 CALL  SUB_1

4.
 BSF   GPIO, BIT1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is ¡°flushed¡± from the pipeline while the new instruction is being fetched and then executed.

PIC12C5XX

4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP AND STACK   
PIC12C5XX memory is organized into program mem
ory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC12C509, PIC12C509A, PICCR509A and PIC12CE519 with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).
4.1 Program Memory Organization
The PIC12C5XX devices have a 12-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC12C508, PIC12C508A and PIC12CE518 and 1K x 12 (0000h-03FFh) for the PIC12C509, PIC12C509A, PIC12CR509A, and PIC12CE519 are physically implemented. Refer to Figure 4-1. Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC12C508,
PIC12C508A and PIC12CE518) or 1K x 12 space (PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519). The effective reset vector is at 000h, (see Figure 4-1). Location 01FFh (PIC12C508, PIC12C508A and PIC12CE518) or location 03FFh
(PIC12C509, PIC12C509A, PIC12CR509A and

01FFh
0200h
03FFh 0400h
7FFh
PIC12CE519) contains the internal clock oscillator calibration value. This value should never be overwritten.
Note 1: Address 0000h becomes the effective reset vector.  Location 01FFh (PIC12C508, PIC12C508A, PIC12CE518) or location 03FFh (PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519) contains the MOVLW XX INTERNAL RC oscillator calibration value.

PIC12C5XX

4.2 Data Memory Organization
Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers.
The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options.
The general purpose registers are used for data and control information under command of the instructions.
For the PIC12C508, PIC12C508A and PIC12CE518, the register file is composed of 7 special function registers and 25 general purpose registers (Figure 42).
For the PIC12C509, PIC12C509A, PIC12CR509A, and PIC12CE519 the register file is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (Figure 4-3).
4.2.1 GENERAL PURPOSE REGISTER FILE
The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section 4.8).
File Address
00h 01h 02h 03h 04h 05h 06h 07h
1Fh

Note 1: Not a physical register. See Section 4.8

FIGURE 4-3: PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519  REGISTER FILE MAP
FSR<6:5>

00 01

File Address

00h 01h 02h 03h 04h 05h 06h
07h
0Fh

INDF(1)  20h Addresses map 
TMR0 
PCL 
STATUS 
2Fh back to addresses in Bank 0. 
FSR 
OSCCAL 
GPIO 
General Purpose Registers 
10h  30h 
General  General 
Purpose  Purpose 
Registers  Registers 
1Fh  3Fh 

Bank 0 Bank 1 Note 1: Not a physical register. See Section 4.8

PIC12C5XX

4.2.2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets.
The special function registers associated with the The Special Function Registers (SFRs) are registers ¡°core¡± functions are described in this section. Those used by the CPU and peripheral functions to control related to the operation of the peripheral features are the operation of the device (Table 4-1). described in the section for each peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Address  Name  Bit 7  Bit 6  Bit 5  Bit 4  Bit 3  Bit 2  Bit 1  Bit 0  Value on Power-On Reset  Value on All Other Resets(2) 
N/A  TRIS  ¡ª  ¡ª  --11 1111  --11 1111 
N/A  OPTION  Contains control bits to configure Timer0, Timer0/WDT prescaler, wake-up on change, and weak pull-ups  1111 1111  1111 1111 
00h  INDF  Uses contents of FSR to address data memory (not a physical register)  xxxx xxxx  uuuu uuuu 
01h  TMR0  8-bit real-time clock/counter  xxxx xxxx  uuuu uuuu 
02h(1)  PCL  Low order 8 bits of PC  1111 1111  1111 1111 
03h  STATUS  GPWUF  ¡ª  PA0  TO  PD  Z  DC  C  0001 1xxx  q00q quuu(3) 
04h  FSR (PIC12C508/ PIC12C508A/ PIC12C518)  Indirect data memory address pointer  111x xxxx  111u uuuu 
04h  FSR (PIC12C509/ PIC12C509A/ PIC12CR509A/ PIC12CE519)  Indirect data memory address pointer  110x xxxx  11uu uuuu 
OSCCAL 
(PIC12C508/ 
05h  PIC12C509)  CAL3  CAL2  CAL1  CAL0  ¡ª  ¡ª  ¡ª  ¡ª  0111 --- uuuu ---
OSCCAL 
(PIC12C508A/ 
PIC12C509A/ 
05h  PIC12CE518/ PIC12CE519/ PIC12CR509A)  CAL5  CAL4  CAL3  CAL2  CAL1  CAL0  ¡ª  ¡ª  1000 00- uuuu uu-
GPIO 
06h  (PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A)  ¡ª  ¡ª  GP5  GP4  GP3  GP2  GP1  GP0  --xx xxxx  --uu uuuu 
GPIO 
(PIC12CE518/ 
06h  PIC12CE519)  SCL  SDA  GP5  GP4  GP3  GP2  GP1  GP0  11xx xxxx  11uu uuuu 

Legend: Shaded boxes = unimplemented or unused, ¡ª = unimplemented, read as ¡¯0¡¯ (if applicable) x = unknown, u = unchanged, q = see the tables in Section 8.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 for an explanation of how to access these bits.
2: Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.
3: If reset was due to wake-up on pin change then bit 7 = 1.  All other resets will cause bit 7 = 0.
PIC12C5XX

4.3 STATUS Register
This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words.
The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
FIGURE 4-4: STATUS REGISTER (ADDRESS:03h)
For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary.

R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
R = Readable bit
W = Writable bit
bit7 6543 2 1 bit0
- n = Value at POR reset bit 7: GPWUF: GPIO reset bit
1 = Reset due to wake-up from SLEEP on pin change
0 = After power up or other reset

bit 6: Unimplemented
bit 5: PA0: Program page preselect bits 1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519 0 = Page 0 (000h - 1FFh) - PIC12C5XX Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products.
bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred
bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred

bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF
1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred

PIC12C5XX

4.4 OPTION Register
The OPTION register is a 8-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits.
Note:  If TRIS bit is set to ¡®0¡¯, the wake-up on 
change and pull-up functions are disabled 
for that pin; i.e., note that TRIS overrides 
OPTION control of GPPU and GPWU. 
Note:  If the T0CS bit is set to ¡®1¡¯, GP2 is forced to 
be an input even if TRIS GP2 = ¡®0¡¯. 

FIGURE 4-5: OPTION REGISTER 

W-1  W-1  W-1  W-1  W-1  W-1  W-1  W-1 
bit7  6  5  4  3  2  1  bit0  W = Writable bit U = Unimplemented bit - n = Value at POR reset Reference Table 4-1 for other resets. 
bit 7:  GPWU: Enable wake-up on pin change (GP0, GP1, GP3) 1 = Disabled 0 = Enabled 
bit 6:  GPPU: Enable weak pull-ups (GP0, GP1, GP3) 1 = Disabled 0 = Enabled 
bit 5:  T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4 
bit 4:  T0SE: Timer0 source edge select bit 1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin 
bit 3:  PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 
bit  2-0:  PS2:PS0: Prescaler rate select bits 

Bit Value Timer0 Rate WDT Rate
000  1 : 2  1 : 1 
001  1 : 4  1 : 2 
010  1 : 8  1 : 4 
011  1 : 16  1 : 8 
100  1 : 32  1 : 16 
101  1 : 64  1 : 32 
110  1 : 128  1 : 64 
111  1 : 256  1 : 128 

PIC12C5XX

4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains four to six bits for calibration.  Increasing the cal value increases the frequency. See Section 7.2.5 for more information on the internal oscillator.

FIGURE 4-7: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508A/C509A/CR509A/12CE518/ 12CE519

PIC12C5XX

4.6 Program Counter
As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 48).
For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-8).
Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5.
Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).

4.6.1 EFFECTS OF RESET
The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XX, the PC will roll over to location 00h, and begin executing user code.
The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected.
Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.
4.7 Stack
PIC12C5XX devices have a 12-bit wide L.I.F.O. hardware push/pop stack.
A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL¡¯s are executed, only the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW¡¯s are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.
Upon any reset, the contents of the stack remain unchanged, however the program counter (PCL) will also be reset to 0.
Note 1: There are no STATUS bits to indicate stack overflows or stack underflow conditions.
Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions.

PIC12C5XX

4.8 Indirect Data Addressing; INDF and FSR Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 4-1: INDIRECT ADDRESSING
. 
Register file 07 contains the value 10h

. 
Register file 08 contains the value 0Ah

. 
Load the value 07 into the FSR register

. 
A read of the INDF register will return the value of 10h

. 
Increment the value of the FSR register by one (FSR = 08)

. 
A read of the INDR register now will return the value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
movlw  0x10  ;initialize pointer 
movwf  FSR  ; to RAM 
NEXT  clrf  INDF  ;clear INDF register 
incf  FSR,F  ;inc pointer 
btfsc  FSR,4  ;all done? 
goto  NEXT  ;NO, clear next 
CONTINUE 
:  ;YES, continue 
The FSR  is  a 5-bit wide  register. It  is  used in 

conjunction with the INDF register to indirectly address the data memory area.
The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.
PIC12C508/PIC12C508A/PIC12CE518: Does not use banking. FSR<7:5> are unimplemented and read as '1's.
PIC12C509/PIC12C509A/PIC12CR509A/ PIC12CE519:  Uses FSR<5>. Selects between bank 0 and bank 1. FSR<7:6> is unimplemented, read as '1¡¯ .
FIGURE 4-9: DIRECT/INDIRECT ADDRESSING Note 1: For register map detail see Section 4.2. Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519. bank location select location select bank select Indirect Addressing Direct Addressing Data Memory(1) 0Fh 10h Bank 0 Bank 1(2) 0456 (FSR) 00 01 00h 1Fh 3Fh (opcode) 0456 (FSR) Addresses map back to addresses in Bank 0.
PIC12C5XX

5.0 I/O PORT
As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O
pins independent of the pin¡¯s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. See Section 7.0 for SCL and SDA description for PIC12CE5XX.
5.1 GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that GP3 is an input only pin. The configuration word can set several I/O¡¯s to alternate functions. When acting as alternate functions the pins will read as ¡®0¡¯ during port read. Pins GP0, GP1, and GP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled.
5.2 TRIS Register
The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and GP2 which may be controlled by the option register, see Figure 4
5.

5.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as
input or output. 
FIGURE 5-1:  EQUIVALENT CIRCUIT 
Data  FOR A SINGLE I/O PIN 

Note 1: I/O pins have protection diodes to VDD and VSS.
Note 2: See Table 3-1 for buffer type.
Note 3: See Section 7.0 for SCL and SDA description for PIC12CE5XX

PIC12C5XX

TABLE 5-1: SUMMARY OF PORT REGISTERS
Address  Name  Bit 7  Bit 6  Bit 5  Bit 4  Bit 3  Bit 2  Bit 1  Bit 0  Value on Power-On Reset  Value on All Other Resets 
N/A  TRIS  ¡ª  ¡ª  --11 1111  --11 1111 
N/A  OPTION  GPWU  GPPU  T0CS  T0SE  PSA  PS2  PS1  PS0  1111 1111  1111 1111 
03H  STATUS  GPWUF  ¡ª  PAO  TO  PD  Z  DC  C  0001 1xxx  q00q quuu(1) 
06h  GPIO (PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A)  ¡ª  ¡ª  GP5  GP4  GP3  GP2  GP1  GP0  --xx xxxx  --uu uuuu 
06h  GPIO (PIC12CE518/ PIC12CE519)  SCL  SDA  GP5  GP4  GP3  GP2  GP1  GP0  11xx xxxx  11uu uuuu 

Legend: Shaded cells not used by Port Registers, read as ¡®0¡¯, ¡ª = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in Section 8.7 for possible values.
Note 1: If reset was due to wake-up on change, then bit 7 = 1.  All other resets will cause bit 7 = 0.
5.4 I/O Programming Considerations
5.4.1 BI-DIRECTIONAL I/O PORTS
Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.
Example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port.
A pin actively outputting a high or a low should not be driven from external devices at the same time in order
to change the level on this pin (¡°wired-or¡±, ¡°wiredand¡±). The resulting high output currents may damage the chip.
EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;
;  GPIO latch  GPIO pins
;  ----------  ---------
BCF   GPIO, 5  ;--01 -ppp   --11 pppp
 BCF   GPIO, 4  ;--10 -ppp   --11 pppp
  MOVLW 007h  ;
  TRIS  GPIO      ;--10 -ppp   --11 pppp

;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).

5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

PIC12C5XX

FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q4
Q3
Q3
Q3
Q3
Q1 Q2
Q1
Q2
Q1
Q2

Q1
Q2

PC + 3 PC
This example shows a write to GPIO followed
Instruction
by a read from GPIO.
fetched NOP NOP MOVWF GPIO MOVF GPIO,W
Data setup time = (0.25 TCY ¨C TPD) where: TCY = instruction cycle.

GP5:GP0
TPD = propagation delay

Port pin Port pin
Therefore, at higher clock frequencies, a
written here sampled here

write followed by a read may be problematic.
Instruction executed

NOP (Write to
MOVWF GPIO MOVF GPIO,W
(Read
GPIO)

GPIO)

PIC12C5XX

NOTES:

PIC12C5XX

6.0 TIMER0 MODULE AND TMR0 REGISTER
The Timer0 module has the following features:
. 
8-bit timer/counter register, TMR0 -Readable and writable

. 
8-bit software programmable prescaler

. 
Internal or external clock select -Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0 module.
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Fig