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ALLEGRO A6832SEP-T DABiC-5 32-Bit Serial Input Latched Sink Drivers!44-pin PLCC package

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Part No.】  A6832SEP-T 
【Category】 DABiC-5 32-Bit Serial Input Latched Sink Drivers
【Packing】   44-pin PLCC
【MFQ】        ALLEGRO
【Datasheet】A6832SEP-T Datasheet

Contact person:

Frances New

Phone:+86-755-81832961

Fax:+86-755-83299282

Email:sumzi@sumzi.com

MSN:sumzi-frances@msn.com

http://www.sumzi.com

Pin-Out or Package

Features

  • 3.3 V to 5 V logic supply range
  • To 10 MHz data input rate
  • Schmitt trigger inputs for improved noise immunity
  • Low-power CMOS logic and latches
  • 40 V current sink outputs
  • Low saturation voltage
  • -40°C operation available

Applications

  • Thermal printheads
  • Multiplexed LED displays
  • Incandescent lamps

Pb (lead) free

Description

Intended originally to drive thermal printheads, the A6832 has been optimized for low output-saturation voltage, high-speed operation, and pin configurations that are the most convenient for the tight space requirements of high-resolution printheads. These integrated circuits can also be used to drive multiplexed LED displays or incandescent lamps at up to 125 mA peak current. The combination of bipolar and MOS technologies gives the A6832 arrays an interface flexibility beyond the reach of standard buffers and power driver circuits.

The devices each have 32 bipolar NPN open-collector saturated drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS shift registers, and CMOS control circuitry. The high-speed CMOS shift registers and latches allow operation with most microprocessor-based systems. Use of these drivers with TTL may require input pull-up resistors to ensure an input logic high. MOS serial data outputs permit cascading for interface applications requiring additional drive lines.

The A6832 is supplied in a 44-lead plastic leaded chip carrier (package suffix EP), for surface-mount applications requiring minimum area. These devices are lead (Pb) free, with 100% matte tin plated leadframes.

Functional Block Diagram

Functional Block Diagram 

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