New eSilicon Peripheral Subsystem offers Design Flexibility for ARM Processor-Based Chips

SUNNYVALE, Calif. ¡ª July 2, 2007 - eSilicon Corporation, a pioneering semiconductor Value Chain Producer (VCP), today announced a new ARM® processor-based peripheral subsystem architecture. The new subsystem reduces time-to-market for ARM Powered® system-on-chip (SoC) solutions by providing developers with several industry-proven, ¡°off-the-shelf¡± system technologies, enabling them to focus on their application-specific, value-added functions.

¡°In today¡¯s fast-paced environment, customers can reduce their risk and design cycle times by utilizing pre-verified peripheral subsystems built around ARM processors,¡± said Hugh Durdan, VP of Marketing, eSilicon. ¡°eSilicon¡¯s peripheral subsystem not only allows customers to focus their design efforts on the unique, differentiating aspects of their chip, but also enables them to quickly offer derivative chips by making modifications to the peripheral subsystem to support different industry standard interfaces.¡±

¡°ARM is committed to working with market leaders like eSilicon to provide chip developers with optimized solutions for bringing ARM processor-based designs to market as efficiently as possible,¡± said Kevin McDermott, director of CPU product marketing, Processor Division, ARM. ¡°The ARM7™ and ARM9™ families of processors are widely adopted in a large variety of applications today and in this rapidly evolving marketplace, it is imperative that companies stay ahead by delivering trusted and cost-effective products. eSilicon¡¯s new peripheral subsystem for ARM Powered SoC solutions further strengthens our partnership and enables OEMs to bring ARM7 and ARM9 family-based designs to volume quickly. With eSilicon¡¯s peripheral subsystem, design teams can now be more agile in keeping up with market demands.¡±

The new subsystem, which can be used as-is or customized for specific applications, is built around the ARM7TDMI® and ARM926EJ™ processors that offer a robust, quick turnaround choice for many application areas like wireless technologies, mobile storage devices and set-top boxes. This new subsystem makes system design based on these processors even quicker by including several standard functions including memory controllers, serial ports, interrupt controllers, timers, real-time clock, PLL and low-speed ADC. The subsystem is designed in single- and multi-AHB (AMBA® High-performance Bus) configurations, making it easy to accommodate specialty IP including PCI, USB, Ethernet, 802.11 and Bluetooth. This provides chip developers with the ability to modify the subsystem in-house, or work directly with eSilicon to optimize the subsystem for their application. eSilicon also offers an extensive verification environment that covers basic boot and CPU tests, as well as integration tests for all built-in, standard functions.

The eSilicon® peripheral subsystem solution includes:

• ARM DSM models for simulation (Solaris or Linux, supporting Verilog-XL, NC-Verilog, VCS, ModelSim)
• Timing models (.lib and SDF)
• Cadence LEF files for the ARM core
• Synthesizable RTL source code for the subsystem (excluding the core)
• Synopsys synthesis scripts
• Verification test bench
• Drivers and monitors