The SPI-4.2 LogiCORE IP interconnects physical-layer ASSPs to link layer FPGA devices in a wide range of networking applications and multiservice DWDM and SONET/SDH-based transport systems. It is fully compliant with the OIF SPI-4.2 standard, provides proven interoperability with industry-leading ASSPs, and yields up to 20% higher data bandwidth due to optimized payload efficiencies, compared to competing FPGA offerings.

The reference design uses Virtex-5 LXT FPGAs, the ML550 hardware verification board, the SPI-4.2 LogiCORE IP, and a SerDes Framer Interface SFI-4.1 reference design. It supports up to 710 Mbits/s/channel with dynamic alignment to provide OC-192 framer interfaces. Verified across multiple FPGA platforms, the solutions accelerate the design cycle of wired networking systems that require OC-192 (10-Gbit/s), multiple OC-48 (2.5-Gbit/s), or 10-Gbit/s Ethernet interfaces