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ON PLL-based ICs create ultra-low jitter clocks

发布时间:2008-01-08 浏览:3851次
 

The NB3N3002 and NB3N5573 3.3 v clock generators create selectable 25, 100, 125, and 200 MHz clocks with host clock signal levels (HCSL) and sub-ps jitter. They target PCI Express, GigaBit Ethernet, and FBDIMM applications.

The NB3N3002 generates one differential HCSL output clock, while the NB3N5573 delivers dual outputs and improved jitter performance. They use a low cost 25 MHz crystal and yield clocks with phase noise of -130 dBc/Hz, relative to the carrier, at a 100 KHz offset and come in a 5.0 x 4.4 mm TSSOP-16 package.

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