A8904SLB ÏìÄ´Ö¸¹«Ë¾ ÌṩӢÎÄ×ÊÁÏ

ѯ¼ÛÈÈÏߣº

0755£­83283733, 83031813£¬33062500

QQ£º623069669

MSN£ºsumzi003@sumzi.com  sumzi006@sumzi.com

Email:sumzi@sumzi.com 

http://www.sumzi.com

A8904
Three-Phase Brushless DC Motor Controller/Driver with Back-EMF Sensing

Features

• Pin-for-pin replacement for A8902CLBA
• Start-up commutation circuitry
• Sensorless commutation circuitry
• Option of external sector data tachometer signal
• Option of external speed control
• Oscillator operation up to 20 MHz
• Programmable overcurrent limit
• Transconductance gain options: 500 mA/V or 250 mA/V
• Programmable watchdog timer
• Directional control
• Serial port interface
• TTL-compatible inputs
• System diagnostics data-out ported in real time
• Dynamic braking through serial port or external terminal

Description

The A8904 is a 3-phase brushless DC motor controller/driver designed for applications where accurate control of high-speed motors is required. The three half-bridge outputs are low on-resistance, N-channel DMOS devices capable of driving up to 1.2 A. The A8904 provides complete, reliable, self-contained back EMF sensing, motor start-up, and running algorithms. A programmable digital frequency-locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation.

A serial port allows the user to program various features and modes of operation, such as the speed control parameters, start-up current limit, sleep mode, direction, and diagnostic modes.

The A8904 is fabricated in the Allegro® BCD (Bipolar CMOS DMOS) process, an advanced mixed-signal technology that combines bipolar, analog, and digital CMOS, with DMOS power devices.

The device is provided in a 24-pin wide-body SOIC package, with 4 internally-fused leads for enhanced thermal dissipation (package LB), and a thin (<1.2 mm overall height), 28-pin TSSOP package with an exposed thermal pad Package LP). Both packages are lead (Pb) free, with 100% matte tin leadframe plating.

• APEK8904 Demo Board Software Download (10 MB ZIP)

Functional Block Diagram