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The PPS Gen 2 (80KSW0001) preprocessing switch provides interconnect and acceleration functions needed by 3G wireless systems. The chip boosts base station performance by up to 20% by offloading DSPs, FPGAs, or ASICs of certain bandwidth-intensive tasks, freeing the DSPs to execute higher value-added and differentiating algorithms and reducing the cost of custom logic.

The 676-ball 27 x 27-mm or 324-ball 19 x 19-mm flip-chip packaged device distributes data to multiple DSPs and supports four preprocessing blocks via three 4x SRIO ports, or up to twelve 1x ports. Each port can be configured for 3.125, 2.5, or 1.25 Gbaud, and the chip is compatible with ATCA and MicroTCA standards.