NEC jumpstarts 40nm process, eDRAM tech

NEC ElectronicsCorp. has unveiled a 40nm logic process that makes use of a one-two punch: hafnium-based high-k dielectric materials and nickel-silicide gate electrodes. The process, to be shipped in the 2009 time frame, also uses zirconium-oxide DRAM capacitors.

The company and Toshiba Corp. are co-developing a 45nm process, as part of a previously-announced partnership, but NEC is said to be tweaking the process and will roll out its own version, which will be a 40nm offering.

NEC also included high-k dielectric materials for gate-stack applications within its recently-introduced, 55nm process, dubbed UX7LSeD. Like the 55nm process, NEC has also incorporated an embedded DRAM (eDRAM) technology into the mix¡ªthe UX8GD and UX8LD.

The UX8GD eDRAM technology boasts clock speeds up to 800MHz and low operating power, making it suitable for digital video cameras, game consolesand other consumer applications.

Meanwhile, the UX8LD eDRAM technology features low leakage-current levels that reduce power consumption by as much two-thirds compared to equivalent SRAM in the marketplace, making it suitable for use in mobile handsetsand other portable devices that require low standby power.

Both eDRAM offerings are available in memory configurations up to 256Mbit. Cell size is 0.06µm², 50 percent smaller than the company's previous 55nm offering.

NEC began shipment of 55nm eDRAM samples in October 2007 and plans to ramp to volume production by the end of this fiscal year, Mar. 31, 2008. Volume production of 40nm devices is scheduled to begin by the end of the next fiscal year at NEC's 300mmwafer line in Yamagata.